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ASoC: cs42l42: Add PLL ratio table values
authorVitaly Rodionov <vitalyr@opensource.cirrus.com>
Wed, 24 May 2023 12:52:36 +0000 (13:52 +0100)
committerMark Brown <broonie@kernel.org>
Thu, 25 May 2023 09:54:22 +0000 (10:54 +0100)
commit13e75f4b03217226f110c5bb5d11720adb5ca9d1
treee48dc98b332ebbd435d9a26b5edf9341c44a2399tree | snapshot
parentf9f46d05003ea6120fa27e01628770a2dac0fa75commit | diff
ASoC: cs42l42: Add PLL ratio table values

Add 4.8Mhz 9.6Mhz and 19.2MHz SCLK values
for MCLK 12MHz and 12.288MHz requested by Intel.

Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230524125236.57149-1-vitalyr@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/cs42l42.c diff | blob | history
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