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iommu/amd: Do not set the D bit on AMD v2 table entries
authorJason Gunthorpe <jgg@nvidia.com>
Fri, 30 Aug 2024 00:06:23 +0000 (21:06 -0300)
committerJoerg Roedel <jroedel@suse.de>
Wed, 4 Sep 2024 09:39:03 +0000 (11:39 +0200)
commit2910a7fa1be090fc7637cef0b2e70bcd15bf5469
tree8a8e2fde1ae893d3f6ae78db5c79c6f5e632e649tree | snapshot
parent7e515866299d1d01db6c2bbbc8045218c099ba1fcommit | diff
iommu/amd: Do not set the D bit on AMD v2 table entries

The manual says that bit 6 is IGN for all Page-Table Base Address
pointers, don't set it.

Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table")
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/14-v2-831cdc4d00f3+1a315-amd_iopgtbl_jgg@nvidia.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/amd/io_pgtable_v2.c diff | blob | history
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