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(parent: 971f128) | patch
dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
authorEmil Renner Berthing <emil.renner.berthing@canonical.com>
Tue, 31 Oct 2023 14:14:43 +0000 (15:14 +0100)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 22 Nov 2023 11:58:08 +0000 (11:58 +0000)
commit3d70b9853b44d3f034acaf5e3be7d5228daddef4
tree4107271f266deb65b4fc905df2cec046bfebff22tree | snapshot
parent971f128bb2d9314203d365b7f163a5c35167bb6bcommit | diff
dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible

This cache controller is also used on the StarFive JH7100 SoC.
Unfortunately it needs a quirk to work properly, so add dedicated
compatible string to be able to match it.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml diff | blob | history
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