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(parent: 9e1ff30) | patch
drm/amd/display: Fix B0 USB-C DP Alt mode
authorLiu, Zhan <Zhan.Liu@amd.com>
Thu, 9 Sep 2021 17:26:37 +0000 (13:26 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 5 Oct 2021 14:17:32 +0000 (10:17 -0400)
commit45d65c0f09aaa6cdd21fe0743f317d4bbdfd1466
treefb87ddbf7d87f9c028c47a00cbc1396438f34243tree | snapshot
parent9e1ff307c779ce1f0f810c7ecce3d95bbae40896commit | diff
drm/amd/display: Fix B0 USB-C DP Alt mode

[Why]
Starting from B0, along with RDPCSTX, RDPCSPIPE registers are also used.

[How]
Make sure RDPCSPIPE registers are programmed correctly.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
(cherry picked from commit bdd1a21b52557ea8f61d0a5dc2f77151b576eb70)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h diff | blob | history
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