]> git-server-git.apps.pok.os.sepia.ceph.com Git - ceph-client.git/commit
drm/i915/color: Place 3D LUT after CSC in plane color pipeline
authorChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Tue, 13 Jan 2026 10:22:51 +0000 (15:52 +0530)
committerMaarten Lankhorst <dev@lankhorst.se>
Thu, 22 Jan 2026 09:24:30 +0000 (10:24 +0100)
commit7261305d22a729fb7f8a3187414c145a492787d4
treefb9756cb4e1194b709646e58daf3a572b79c89ac
parent604826acb3f53c6648a7ee99a3914ead680ab7fb
drm/i915/color: Place 3D LUT after CSC in plane color pipeline

Move the 3D LUT block to its correct position in the plane
color pipeline:

  [Pre-CSC] -> [CSC] -> [3DLUT] -> [Post-CSC]

Fixes: 65db7a1f9cf7 ("drm/i915/color: Add 3D LUT to color pipeline")
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260113102303.724205-2-chaitanya.kumar.borah@intel.com
drivers/gpu/drm/i915/display/intel_color_pipeline.c