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(parent: 06c2afb) | patch
clk: rockchip: rk3568: Add PLL rate for 101MHz
authorAlibek Omarov <a1ba.omarov@gmail.com>
Wed, 14 Jun 2023 13:47:16 +0000 (16:47 +0300)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 10 Jul 2023 10:11:26 +0000 (12:11 +0200)
commit7f890a885f9a226ae1309b967d4e6fac933610db
tree4846acfe4a11a59e985ad157e6d38324027d76cetree | snapshot
parent06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5commit | diff
clk: rockchip: rk3568: Add PLL rate for 101MHz

This patch adds PLL setting for not so common resolution as 1920x720-50.00,
which can be set using 2500 horizontal signals and 808 vertical.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20230614134716.1055862-1-a1ba.omarov@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3568.c diff | blob | history
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