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drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition
authorJouni Högander <jouni.hogander@intel.com>
Mon, 14 Apr 2025 10:04:58 +0000 (13:04 +0300)
committerJouni Högander <jouni.hogander@intel.com>
Wed, 23 Apr 2025 09:16:26 +0000 (12:16 +0300)
commitb23c157d46d1f1c7c96dde83dedb6e1f298fff26
tree7c3cb8ce1520e0f7b0c49e646c2cbc491b515003tree | snapshot
parenta99b050ca7f48505d7f59de4b2be46cbd2b6c048commit | diff
drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition

To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register
definitions.

Bspec: 67576

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-4-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_dmc_regs.h diff | blob | history
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