]> git-server-git.apps.pok.os.sepia.ceph.com Git - ceph-client.git/commit
drm/i915/dsc: Add Selective Update register definitions
authorJouni Högander <jouni.hogander@intel.com>
Wed, 4 Mar 2026 11:30:09 +0000 (13:30 +0200)
committerTvrtko Ursulin <tursulin@ursulin.net>
Tue, 10 Mar 2026 08:22:10 +0000 (08:22 +0000)
commitc2c79c6d5b939ae8a42ddb884f576bddae685672
tree5637fa1772848bed8f1f9c2aef08b0061797df4c
parent1be2fca84f520105413d0d89ed04bb0ff742ab16
drm/i915/dsc: Add Selective Update register definitions

Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
Transport configuration.

Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com
(cherry picked from commit 24f96d903daf3dcf8fafe84d3d22b80ef47ba493)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
drivers/gpu/drm/i915/display/intel_vdsc_regs.h