PCI/ASPM: Move LTR path check to where it's used

pcie_get_aspm_reg() mostly reads ASPM-related registers, but in some cases
it also updates the value read from PCI_L1SS_CAP based on LTR properties.

Move this update to the point where the value is used to make the code more
readable.

No functional change intended, although previously we could clear
PCI_L1SS_CAP_ASPM_L1_2 for both ends of the link, and now we'll only do it
for the downstream end of a link.  This shouldn't matter because we always
test that bit by ANDing l1ss_cap for the upstream and downstream ends.

Link: https://lore.kernel.org/r/20201015193039.12585-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 237a423e53ae8532b86feee85cd25f58bb6f2e74..386b45eb79ba78bb6d564926a0d400b2529bbab8 100644 (file)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -418,14 +418,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev,
                return;
        }
 
-       /*
-        * If we don't have LTR for the entire path from the Root Complex
-        * to this device, we can't use ASPM L1.2 because it relies on the
-        * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.
-        */
-       if (!pdev->ltr_path)
-               info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
-
        pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
                              &info->l1ss_ctl1);
        pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
@@ -612,7 +604,14 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
        link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
        link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
 
-       /* Setup L1 substate */
+       /* Setup L1 substate
+        * If we don't have LTR for the entire path from the Root Complex
+        * to this device, we can't use ASPM L1.2 because it relies on the
+        * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.
+        */
+       if (!child->ltr_path)
+               dwreg.l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
+
        if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
                link->aspm_support |= ASPM_STATE_L1_1;
        if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)