#define OHCI_PARAM_DEBUG_AT_AR         1
 #define OHCI_PARAM_DEBUG_SELFIDS       2
 #define OHCI_PARAM_DEBUG_IRQS          4
-#define OHCI_PARAM_DEBUG_BUSRESETS     8 /* only effective before chip init */
+#define OHCI_PARAM_DEBUG_BUSRESETS     8
 
 static int param_debug;
 module_param_named(debug, param_debug, int, 0644);
 
        ohci->generation = generation;
        reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
-       if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
-               reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
+       reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
 
        if (ohci->quirks & QUIRK_RESET_PACKET)
                ohci->request_generation = generation;
        reg_write(ohci, OHCI1394_IntEventClear,
                  event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
        log_irqs(ohci, event);
+       // The flag is masked again at bus_reset_work() scheduled by selfID event.
        if (event & OHCI1394_busReset)
                reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
 
                OHCI1394_cycleInconsistent |
                OHCI1394_unrecoverableError |
                OHCI1394_cycleTooLong |
-               OHCI1394_masterIntEnable;
-       if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
-               irqs |= OHCI1394_busReset;
+               OHCI1394_masterIntEnable |
+               OHCI1394_busReset;
        reg_write(ohci, OHCI1394_IntMaskSet, irqs);
 
        reg_write(ohci, OHCI1394_HCControlSet,