void bdx_uncore_cpu_init(void)
 {
+       int pkg = topology_phys_to_logical_pkg(0);
+
        if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
                bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
        uncore_msr_uncores = bdx_msr_uncores;
 
        /* BDX-DE doesn't have SBOX */
-       if (boot_cpu_data.x86_model == 86)
+       if (boot_cpu_data.x86_model == 86) {
                uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
+       /* Detect systems with no SBOXes */
+       } else if (uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]) {
+               struct pci_dev *pdev;
+               u32 capid4;
 
+               pdev = uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3];
+               pci_read_config_dword(pdev, 0x94, &capid4);
+               if (((capid4 >> 6) & 0x3) == 0)
+                       bdx_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
+       }
        hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints;
 }
 
                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46),
                .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2),
        },
+       { /* PCU.3 (for Capability registers) */
+               PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fc0),
+               .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
+                                                  HSWEP_PCI_PCU_3),
+       },
        { /* end: all zeroes */ }
 };