]> git.apps.os.sepia.ceph.com Git - ceph-client.git/commitdiff
ARM: dts: microchip: sama7d65: Add gmac interfaces for sama7d65 SoC
authorRyan Wanner <Ryan.Wanner@microchip.com>
Tue, 1 Apr 2025 16:13:18 +0000 (09:13 -0700)
committerClaudiu Beznea <claudiu.beznea@tuxon.dev>
Fri, 16 May 2025 05:31:26 +0000 (08:31 +0300)
Add support for GMAC interfaces on SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/05b107796b6f3a173d0dd0a5b2107b675cfd994e.1743523114.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
arch/arm/boot/dts/microchip/sama7d65.dtsi

index b6710ccd4c360bdde1ecc05d4ac78cff501bcb2c..cd17b838e179eecf89673f0bdd408eba132fe3a2 100644 (file)
                        status = "disabled";
                };
 
+               gmac0: ethernet@e1618000 {
+                       compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem";
+                       reg = <0xe1618000 0x2000>;
+                       interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>;
+                       clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+                       assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>;
+                       assigned-clock-rates = <125000000>, <200000000>;
+                       status = "disabled";
+               };
+
+               gmac1: ethernet@e161c000 {
+                       compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem";
+                       reg = <0xe161c000 0x2000>;
+                       interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>;
+                       clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+                       assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>;
+                       assigned-clock-rates = <125000000>, <200000000>;
+                       status = "disabled";
+               };
+
                pit64b0: timer@e1800000 {
                        compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
                        reg = <0xe1800000 0x100>;