]> git.apps.os.sepia.ceph.com Git - ceph-client.git/commitdiff
PCI: xilinx: Fix NULL pointer dereference in xilinx_pcie_intr_handler()
authorNam Cao <namcao@linutronix.de>
Mon, 11 Aug 2025 05:41:44 +0000 (07:41 +0200)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 12 Aug 2025 16:31:24 +0000 (11:31 -0500)
f29861aa301c5 ("PCI: xilinx: Switch to msi_create_parent_irq_domain()")
changed xilinx_pcie::msi_domain from child devices' interrupt domain to
Xilinx AXI bridge's interrupt domain.

However, xilinx_pcie_intr_handler() wasn't changed and still reads Xilinx
AXI bridge's interrupt domain from xilinx_pcie::msi_domain->parent. This
pointer is NULL now.

Update xilinx_pcie_intr_handler() to read the correct interrupt domain
pointer.

Fixes: f29861aa301c5 ("PCI: xilinx: Switch to msi_create_parent_irq_domain()")
Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250811054144.4049448-1-namcao@linutronix.de
drivers/pci/controller/pcie-xilinx.c

index f121836c3cf4e46e78ba5adbd98ff85d837b74e7..937ea6ae1ac4863870b3192af11cf7477e91d15f 100644 (file)
@@ -400,7 +400,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
                if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
                        val = pcie_read(pcie, XILINX_PCIE_REG_RPIFR2) &
                                XILINX_PCIE_RPIFR2_MSG_DATA;
-                       domain = pcie->msi_domain->parent;
+                       domain = pcie->msi_domain;
                } else {
                        val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
                                XILINX_PCIE_RPIFR1_INTR_SHIFT;