drm/amd/display: program PSR2 DPCD Configuration

[Why]
To support PSR2 Source DPCD configuration

[How]
Update the PSR2 Source DPCD settings while the PSR2 enabled

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 55a8f58ee23921955e8929cb87473567d74bb6f4..97bb2d8764269265b4beff4e2fc341e6ab5b1cc4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3206,6 +3206,7 @@ bool dc_link_setup_psr(struct dc_link *link,
        unsigned int panel_inst;
        /* updateSinkPsrDpcdConfig*/
        union dpcd_psr_configuration psr_configuration;
+       union dpcd_alpm_configuration alpm_configuration;
 
        psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
@@ -3231,7 +3232,7 @@ bool dc_link_setup_psr(struct dc_link *link,
                        psr_config->psr_frame_capture_indication_req;
 
        /* Check for PSR v2*/
-       if (psr_config->psr_version == 0x2) {
+       if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
                /* For PSR v2 selective update.
                 * Indicates whether sink should start capturing
                 * immediately following active scan line,
@@ -3242,6 +3243,14 @@ bool dc_link_setup_psr(struct dc_link *link,
                 * IRQ_HPD when CRC mismatch is detected.
                 */
                psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
+               /* For PSR v2, set the bit when the Source device will
+                * be enabling PSR2 operation.
+                */
+               psr_configuration.bits.ENABLE_PSR2    = 1;
+               /* For PSR v2, the Sink device must be able to receive
+                * SU region updates early in the frame time.
+                */
+               psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
        }
 
        dm_helpers_dp_write_dpcd(
@@ -3251,6 +3260,18 @@ bool dc_link_setup_psr(struct dc_link *link,
                &psr_configuration.raw,
                sizeof(psr_configuration.raw));
 
+       if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
+               memset(&alpm_configuration, 0, sizeof(alpm_configuration));
+
+               alpm_configuration.bits.ENABLE = 1;
+               dm_helpers_dp_write_dpcd(
+                       link->ctx,
+                       link,
+                       DP_RECEIVER_ALPM_CONFIG,
+                       &alpm_configuration.raw,
+                       sizeof(alpm_configuration.raw));
+       }
+
        psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
        psr_context->transmitterId = link->link_enc->transmitter;
        psr_context->engineId = link->link_enc->preferred_engine;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index d8433c67920126e36152876a9559649bfcf82a13..6e6bd007babc12aae062de6d955b5ce97b3fad85 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -85,7 +85,18 @@ union dpcd_psr_configuration {
                unsigned char LINE_CAPTURE_INDICATION   : 1;
                /* For eDP 1.4, PSR v2*/
                unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
-               unsigned char RESERVED                  : 2;
+               unsigned char ENABLE_PSR2               : 1;
+               /* For eDP 1.5, PSR v2 w/ early transport */
+               unsigned char EARLY_TRANSPORT_ENABLE    : 1;
+       } bits;
+       unsigned char raw;
+};
+
+union dpcd_alpm_configuration {
+       struct {
+               unsigned char ENABLE                    : 1;
+               unsigned char IRQ_HPD_ENABLE            : 1;
+               unsigned char RESERVED                  : 6;
        } bits;
        unsigned char raw;
 };