arm64: dts: qcom: sa8775p: Add support for clock controllers

Add support for video, camera, display0 and display1 clock controllers
on SA8775P. The dispcc1 will be enabled based on board requirements.

Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241025-sa8775p-mm-v4-resend-patches-v6-2-329a2cac09ae@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9f315a51a7c14cd4116ec5a66a60285361d343f1..b64ed5ddafde3e7ec78695fdef0777f1f8457c89 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3759,6 +3759,47 @@
                        interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               videocc: clock-controller@abf0000 {
+                       compatible = "qcom,sa8775p-videocc";
+                       reg = <0x0 0x0abf0000 0x0 0x10000>;
+                       clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>,
+                                <&sleep_clk>;
+                       power-domains = <&rpmhpd SA8775P_MMCX>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               camcc: clock-controller@ade0000 {
+                       compatible = "qcom,sa8775p-camcc";
+                       reg = <0x0 0x0ade0000 0x0 0x20000>;
+                       clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>,
+                                <&sleep_clk>;
+                       power-domains = <&rpmhpd SA8775P_MMCX>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               dispcc0: clock-controller@af00000 {
+                       compatible = "qcom,sa8775p-dispcc0";
+                       reg = <0x0 0x0af00000 0x0 0x20000>;
+                       clocks = <&gcc GCC_DISP_AHB_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>,
+                                <&sleep_clk>,
+                                <0>, <0>, <0>, <0>,
+                                <0>, <0>, <0>, <0>;
+                       power-domains = <&rpmhpd SA8775P_MMCX>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sa8775p-pdc", "qcom,pdc";
                        reg = <0x0 0x0b220000 0x0 0x30000>,
@@ -4381,6 +4422,22 @@
                        };
                };
 
+               dispcc1: clock-controller@22100000 {
+                       compatible = "qcom,sa8775p-dispcc1";
+                       reg = <0x0 0x22100000 0x0 0x20000>;
+                       clocks = <&gcc GCC_DISP_AHB_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>,
+                                <&sleep_clk>,
+                                <0>, <0>, <0>, <0>,
+                                <0>, <0>, <0>, <0>;
+                       power-domains = <&rpmhpd SA8775P_MMCX>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+                       status = "disabled";
+               };
+
                ethernet1: ethernet@23000000 {
                        compatible = "qcom,sa8775p-ethqos";
                        reg = <0x0 0x23000000 0x0 0x10000>,