INTEL_RKL_IDS(&gen11_early_ops),
        INTEL_ADLS_IDS(&gen11_early_ops),
        INTEL_ADLP_IDS(&gen11_early_ops),
+       INTEL_ADLN_IDS(&gen11_early_ops),
        INTEL_RPLS_IDS(&gen11_early_ops),
 };
 
 
        IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_ADLS_RPLS(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
+#define IS_ADLP_N(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
                                    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
 
        INTEL_RKL_IDS(&rkl_info),
        INTEL_ADLS_IDS(&adl_s_info),
        INTEL_ADLP_IDS(&adl_p_info),
+       INTEL_ADLN_IDS(&adl_p_info),
        INTEL_DG1_IDS(&dg1_info),
        INTEL_RPLS_IDS(&adl_s_info),
        {0, 0, 0}
 
        INTEL_ICL_PORT_F_IDS(0),
 };
 
+static const u16 subplatform_n_ids[] = {
+       INTEL_ADLN_IDS(0),
+};
+
 static const u16 subplatform_rpls_ids[] = {
        INTEL_RPLS_IDS(0),
 };
        } else if (find_devid(devid, subplatform_portf_ids,
                              ARRAY_SIZE(subplatform_portf_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_PORTF);
+       } else if (find_devid(devid, subplatform_n_ids,
+                               ARRAY_SIZE(subplatform_n_ids))) {
+               mask = BIT(INTEL_SUBPLATFORM_N);
        } else if (find_devid(devid, subplatform_rpls_ids,
                              ARRAY_SIZE(subplatform_rpls_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_RPL_S);
 
 /* ADL-S */
 #define INTEL_SUBPLATFORM_RPL_S        0
 
+/* ADL-P */
+#define INTEL_SUBPLATFORM_N    0
+
 enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 
        INTEL_VGA_DEVICE(0x46C2, info), \
        INTEL_VGA_DEVICE(0x46C3, info)
 
+/* ADL-N */
+#define INTEL_ADLN_IDS(info) \
+       INTEL_VGA_DEVICE(0x46D0, info), \
+       INTEL_VGA_DEVICE(0x46D1, info), \
+       INTEL_VGA_DEVICE(0x46D2, info)
+
 /* RPL-S */
 #define INTEL_RPLS_IDS(info) \
        INTEL_VGA_DEVICE(0xA780, info), \