drm/amd/display: Expose functions of other dcn use

[Why & HOw]
Expose some functions for later dcns to reuse

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index 663a18ee51628a08137ea9760d3d803a493c27e3..3063b6ab32e5fa459a6fecaa5aee5c582c4835d4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -595,16 +595,6 @@ void dccg401_set_dp_dto(
 
        bool enable = false;
 
-       if (params->otg_inst > 3) {
-               /* dcn401 only has 4 instances */
-               BREAK_TO_DEBUGGER();
-               return;
-       }
-       if (!params->refclk_hz) {
-               BREAK_TO_DEBUGGER();
-               return;
-       }
-
        if (!dc_is_tmds_signal(params->signal)) {
                uint64_t dto_integer;
                uint64_t dto_phase_hz;
@@ -612,6 +602,11 @@ void dccg401_set_dp_dto(
 
                enable = true;
 
+               if (!params->refclk_hz) {
+                       BREAK_TO_DEBUGGER();
+                       return;
+               }
+
                /* Set DTO values:
                 * int = target_pix_rate / reference_clock
                 * phase = target_pix_rate - int * reference_clock,

diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
index d11afd1ce72a26418270ce056cb7f7e702239065..941dce439e979362c8ddf53e3c2b2295cf0b4f46 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
@@ -41,7 +41,7 @@
 #define FN(reg_name, field_name) \
        hubbub2->shifts->field_name, hubbub2->masks->field_name
 
-static void dcn401_init_crb(struct hubbub *hubbub)
+void dcn401_init_crb(struct hubbub *hubbub)
 {
        struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
 
@@ -1110,7 +1110,7 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub,
        return true;
 }
 
-static void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg)
+void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg)
 {
        struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
 
@@ -1147,7 +1147,7 @@ static void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, un
        }
 }
 
-static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase)
+void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase)
 {
        struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
 
@@ -1170,7 +1170,7 @@ static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned comp
        }
 }
 
-static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst)
+void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst)
 {
        struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
 
@@ -1192,7 +1192,7 @@ static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst)
        }
 }
 
-static bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower)
+bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower)
 {
        struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
 

diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
index b1d9ea9d1c3d614d709f92e3d9673deff5db1281..f487155444299349b4a282ca87bd8ac912c9c367 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
@@ -194,6 +194,11 @@ bool hubbub401_get_dcc_compression_cap(
                const struct dc_dcc_surface_param *input,
                struct dc_surface_dcc_cap *output);
 
+bool dcn401_program_arbiter(
+       struct hubbub *hubbub,
+       struct dml2_display_arb_regs *arb_regs,
+       bool safe_to_lower);
+
 void hubbub401_construct(struct dcn20_hubbub *hubbub2,
        struct dc_context *ctx,
        const struct dcn_hubbub_registers *hubbub_regs,
@@ -203,4 +208,9 @@ void hubbub401_construct(struct dcn20_hubbub *hubbub2,
        int pixel_chunk_size_kb,
        int config_return_buffer_size_kb);
 
+void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg);
+void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase);
+void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst);
+void dcn401_init_crb(struct hubbub *hubbub);
+
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
index 0953acbcc6d4585517bc3caac4d02b5049677e72..5aafd0eedf6684d05772a0f78ae125e22d0b23c6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
@@ -270,7 +270,7 @@ static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx,
        return true;
 }
 
-static bool optc35_configure_crc(struct timing_generator *optc,
+bool optc35_configure_crc(struct timing_generator *optc,
                                 const struct crc_params *params)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -437,7 +437,7 @@ void optc35_set_drr(
        REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
 }
 
-static void optc35_set_long_vtotal(
+void optc35_set_long_vtotal(
        struct timing_generator *optc,
        const struct long_vtotal_params *params)
 {
@@ -524,7 +524,7 @@ static void optc35_set_long_vtotal(
        }
 }
 
-static void optc35_wait_otg_disable(struct timing_generator *optc)
+void optc35_wait_otg_disable(struct timing_generator *optc)
 {
        struct optc *optc1;
        uint32_t is_master_en;

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
index 5c2cb1f2778382ddccb8604a478de2c4e5bc7e0d..82e0818c8f9f4be03cd4cba8893ddd12a851830c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
@@ -90,4 +90,13 @@ void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);
 
 void optc35_set_drr(struct timing_generator *optc, const struct drr_params *params);
 
+void optc35_set_long_vtotal(
+       struct timing_generator *optc,
+       const struct long_vtotal_params *params);
+
+bool optc35_configure_crc(struct timing_generator *optc,
+                                const struct crc_params *params);
+
+void optc35_wait_otg_disable(struct timing_generator *optc);
+
 #endif /* __DC_OPTC_DCN35_H__ */