drm/i915/gem: Limit the blitter sizes to ensure low preemption latency

Currently we insert a arbitration point every 128MiB during a blitter
copy. At 8GiB/s, this is around 30ms. This is a little on the large side
if we need to inject a high priority work, so reduced it down to 8MiB or
roughly 1ms.

v2: Don't forget both fill/copy.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028203012.14566-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 516e61e992122f0303834392fa678d287fc313e3..51acffd31575df5cb6ffe9f312a758ec6d739703 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
                                         u32 value)
 {
        struct drm_i915_private *i915 = ce->vm->i915;
-       const u32 block_size = S16_MAX * PAGE_SIZE;
+       const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
        struct intel_engine_pool_node *pool;
        struct i915_vma *batch;
        u64 offset;
@@ -201,7 +201,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
                                         struct i915_vma *dst)
 {
        struct drm_i915_private *i915 = ce->vm->i915;
-       const u32 block_size = S16_MAX * PAGE_SIZE;
+       const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
        struct intel_engine_pool_node *pool;
        struct i915_vma *batch;
        u64 src_offset, dst_offset;