MIPS: mobileye: eyeq5: add OLB system-controller node

The OLB ("Other Logic Block") is a system-controller region hosting
clock, reset and pin controllers. It contains registers such as I2C
speed mode that need to be accessible by other nodes.

Remove fixed-clocks previously used; replace references.
Add parent crystal clock, fixed at 30MHz.
Add pin nodes for all functions.
Add mobileye,eyeq5-olb compatible node, hosting clk, reset and pinctrl.
Add reset and pinctrl references to UART nodes.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi
new file mode 100644 (file)
index 0000000..17a342c
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+
+/ {
+       /* Fixed clock */
+       xtal: xtal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <30000000>;
+       };
+
+/* PLL_CPU derivatives */
+       occ_cpu: occ-cpu {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_CPU>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_cpu>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       cpc_clk: cpc-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&si_css0_ref_clk>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       core0_clk: core0-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&si_css0_ref_clk>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       core1_clk: core1-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&si_css0_ref_clk>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       core2_clk: core2-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&si_css0_ref_clk>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       core3_clk: core3-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&si_css0_ref_clk>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       cm_clk: cm-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&si_css0_ref_clk>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       mem_clk: mem-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&si_css0_ref_clk>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       occ_isram: occ-isram {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_CPU>;
+               #clock-cells = <0>;
+               clock-div = <2>;
+               clock-mult = <1>;
+       };
+       isram_clk: isram-clk { /* gate ClkRstGen_isram */
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_isram>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       occ_dbu: occ-dbu {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_CPU>;
+               #clock-cells = <0>;
+               clock-div = <10>;
+               clock-mult = <1>;
+       };
+       si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_dbu>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+/* PLL_VDI derivatives */
+       occ_vdi: occ-vdi {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_VDI>;
+               #clock-cells = <0>;
+               clock-div = <2>;
+               clock-mult = <1>;
+       };
+       vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_vdi>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       occ_can_ser: occ-can-ser {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_VDI>;
+               #clock-cells = <0>;
+               clock-div = <16>;
+               clock-mult = <1>;
+       };
+       can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_can_ser>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       i2c_ser_clk: i2c-ser-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_VDI>;
+               #clock-cells = <0>;
+               clock-div = <20>;
+               clock-mult = <1>;
+       };
+/* PLL_PER derivatives */
+       occ_periph: occ-periph {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_PER>;
+               #clock-cells = <0>;
+               clock-div = <16>;
+               clock-mult = <1>;
+       };
+       periph_clk: periph-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_periph>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       can_clk: can-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_periph>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       spi_clk: spi-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_periph>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       uart_clk: uart-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_periph>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+       };
+       i2c_clk: i2c-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_periph>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+               clock-output-names = "i2c_clk";
+       };
+       timer_clk: timer-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_periph>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+               clock-output-names = "timer_clk";
+       };
+       gpio_clk: gpio-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_periph>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+               clock-output-names = "gpio_clk";
+       };
+       emmc_sys_clk: emmc-sys-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_PER>;
+               #clock-cells = <0>;
+               clock-div = <10>;
+               clock-mult = <1>;
+               clock-output-names = "emmc_sys_clk";
+       };
+       ccf_ctrl_clk: ccf-ctrl-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_PER>;
+               #clock-cells = <0>;
+               clock-div = <4>;
+               clock-mult = <1>;
+               clock-output-names = "ccf_ctrl_clk";
+       };
+       occ_mjpeg_core: occ-mjpeg-core {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_PER>;
+               #clock-cells = <0>;
+               clock-div = <2>;
+               clock-mult = <1>;
+               clock-output-names = "occ_mjpeg_core";
+       };
+       hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_mjpeg_core>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+               clock-output-names = "hsm_clk";
+       };
+       mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
+               compatible = "fixed-factor-clock";
+               clocks = <&occ_mjpeg_core>;
+               #clock-cells = <0>;
+               clock-div = <1>;
+               clock-mult = <1>;
+               clock-output-names = "mjpeg_core_clk";
+       };
+       fcmu_a_clk: fcmu-a-clk {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_PER>;
+               #clock-cells = <0>;
+               clock-div = <20>;
+               clock-mult = <1>;
+               clock-output-names = "fcmu_a_clk";
+       };
+       occ_pci_sys: occ-pci-sys {
+               compatible = "fixed-factor-clock";
+               clocks = <&olb EQ5C_PLL_PER>;
+               #clock-cells = <0>;
+               clock-div = <8>;
+               clock-mult = <1>;
+               clock-output-names = "occ_pci_sys";
+       };
+       pclk: pclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <250000000>;  /* 250MHz */
+       };
+       tsu_clk: tsu-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;  /* 125MHz */
+       };
+};

diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
deleted file mode 100644 (file)
index 78f5533..0000000
--- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright 2023 Mobileye Vision Technologies Ltd.
- */
-
-/ {
-       /* Fixed clock */
-       pll_cpu: pll-cpu {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <1500000000>;
-       };
-
-       pll_vdi: pll-vdi {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <1280000000>;
-       };
-
-       pll_per: pll-per {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <2000000000>;
-       };
-
-       pll_ddr0: pll-ddr0 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <1857210000>;
-       };
-
-       pll_ddr1: pll-ddr1 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <1857210000>;
-       };
-
-/* PLL_CPU derivatives */
-       occ_cpu: occ-cpu {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_cpu>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_cpu>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       cpc_clk: cpc-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&si_css0_ref_clk>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       core0_clk: core0-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&si_css0_ref_clk>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       core1_clk: core1-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&si_css0_ref_clk>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       core2_clk: core2-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&si_css0_ref_clk>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       core3_clk: core3-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&si_css0_ref_clk>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       cm_clk: cm-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&si_css0_ref_clk>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       mem_clk: mem-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&si_css0_ref_clk>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       occ_isram: occ-isram {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_cpu>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-       };
-       isram_clk: isram-clk { /* gate ClkRstGen_isram */
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_isram>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       occ_dbu: occ-dbu {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_cpu>;
-               #clock-cells = <0>;
-               clock-div = <10>;
-               clock-mult = <1>;
-       };
-       si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_dbu>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-/* PLL_VDI derivatives */
-       occ_vdi: occ-vdi {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_vdi>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-       };
-       vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_vdi>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       occ_can_ser: occ-can-ser {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_vdi>;
-               #clock-cells = <0>;
-               clock-div = <16>;
-               clock-mult = <1>;
-       };
-       can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_can_ser>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       i2c_ser_clk: i2c-ser-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_vdi>;
-               #clock-cells = <0>;
-               clock-div = <20>;
-               clock-mult = <1>;
-       };
-/* PLL_PER derivatives */
-       occ_periph: occ-periph {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_per>;
-               #clock-cells = <0>;
-               clock-div = <16>;
-               clock-mult = <1>;
-       };
-       periph_clk: periph-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_periph>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       can_clk: can-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_periph>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       spi_clk: spi-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_periph>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       uart_clk: uart-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_periph>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-       };
-       i2c_clk: i2c-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_periph>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-               clock-output-names = "i2c_clk";
-       };
-       timer_clk: timer-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_periph>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-               clock-output-names = "timer_clk";
-       };
-       gpio_clk: gpio-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_periph>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-               clock-output-names = "gpio_clk";
-       };
-       emmc_sys_clk: emmc-sys-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_per>;
-               #clock-cells = <0>;
-               clock-div = <10>;
-               clock-mult = <1>;
-               clock-output-names = "emmc_sys_clk";
-       };
-       ccf_ctrl_clk: ccf-ctrl-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_per>;
-               #clock-cells = <0>;
-               clock-div = <4>;
-               clock-mult = <1>;
-               clock-output-names = "ccf_ctrl_clk";
-       };
-       occ_mjpeg_core: occ-mjpeg-core {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_per>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-               clock-output-names = "occ_mjpeg_core";
-       };
-       hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_mjpeg_core>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-               clock-output-names = "hsm_clk";
-       };
-       mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
-               compatible = "fixed-factor-clock";
-               clocks = <&occ_mjpeg_core>;
-               #clock-cells = <0>;
-               clock-div = <1>;
-               clock-mult = <1>;
-               clock-output-names = "mjpeg_core_clk";
-       };
-       fcmu_a_clk: fcmu-a-clk {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_per>;
-               #clock-cells = <0>;
-               clock-div = <20>;
-               clock-mult = <1>;
-               clock-output-names = "fcmu_a_clk";
-       };
-       occ_pci_sys: occ-pci-sys {
-               compatible = "fixed-factor-clock";
-               clocks = <&pll_per>;
-               #clock-cells = <0>;
-               clock-div = <8>;
-               clock-mult = <1>;
-               clock-output-names = "occ_pci_sys";
-       };
-       pclk: pclk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <250000000>;  /* 250MHz */
-       };
-       tsu_clk: tsu-clk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <125000000>;  /* 125MHz */
-       };
-};

diff --git a/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi
new file mode 100644 (file)
index 0000000..0b36710
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+/*
+ * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
+ * pin configuration node per function.
+ */
+
+&olb {
+       timer0_pins: timer0-pins {
+               function = "timer0";
+               pins = "PA0", "PA1";
+       };
+       timer1_pins: timer1-pins {
+               function = "timer1";
+               pins = "PA2", "PA3";
+       };
+       timer2_pins: timer2-pins {
+               function = "timer2";
+               pins = "PA4", "PA5";
+       };
+       pps0_pins: pps0-pin {
+               function = "timer2";
+               pins = "PA4";
+       };
+       pps1_pins: pps1-pin {
+               function = "timer2";
+               pins = "PA5";
+       };
+       timer5_ext_pins: timer5-ext-pins {
+               function = "timer5";
+               pins = "PA6", "PA7", "PA8", "PA9";
+       };
+       timer5_ext_input_pins: timer5-ext-input-pins {
+               function = "timer5";
+               pins = "PA6", "PA7";
+       };
+       timer5_ext_incap_a_pins: timer5-ext-incap-a-pin {
+               function = "timer5";
+               pins = "PA6";
+       };
+       timer5_ext_incap_b_pins: timer5-ext-incap-b-pin {
+               function = "timer5";
+               pins = "PA7";
+       };
+       can0_pins: can0-pins {
+               function = "can0";
+               pins = "PA14", "PA15";
+       };
+       can1_pins: can1-pins {
+               function = "can1";
+               pins = "PA16", "PA17";
+       };
+       uart0_pins: uart0-pins {
+               function = "uart0";
+               pins = "PA10", "PA11";
+       };
+       uart1_pins: uart1-pins {
+               function = "uart1";
+               pins = "PA12", "PA13";
+       };
+       spi0_pins: spi0-pins {
+               function = "spi0";
+               pins = "PA18", "PA19", "PA20", "PA21", "PA22";
+       };
+       spi1_pins: spi1-pins {
+               function = "spi1";
+               pins = "PA23", "PA24", "PA25", "PA26", "PA27";
+       };
+       spi1_slave_pins: spi1-slave-pins {
+               function = "spi1";
+               pins = "PA24", "PA25", "PA26";
+       };
+       refclk0_pins: refclk0-pin {
+               function = "refclk0";
+               pins = "PA28";
+       };
+       timer3_pins: timer3-pins {
+               function = "timer3";
+               pins = "PB0", "PB1";
+       };
+       timer4_pins: timer4-pins {
+               function = "timer4";
+               pins = "PB2", "PB3";
+       };
+       timer6_ext_pins: timer6-ext-pins {
+               function = "timer6";
+               pins = "PB4", "PB5", "PB6", "PB7";
+       };
+       timer6_ext_input_pins: timer6-ext-input-pins {
+               function = "timer6";
+               pins = "PB4", "PB5";
+       };
+       timer6_ext_incap_a_pins: timer6-ext-incap-a-pin {
+               function = "timer6";
+               pins = "PB4";
+       };
+       timer6_ext_incap_b_pins: timer6-ext-incap-b-pin {
+               function = "timer6";
+               pins = "PB5";
+       };
+       can2_pins: can2-pins {
+               function = "can2";
+               pins = "PB10", "PB11";
+       };
+       uart2_pins: uart2-pins {
+               function = "uart2";
+               pins = "PB8", "PB9";
+       };
+       spi2_pins: spi2-pins {
+               function = "spi2";
+               pins = "PB12", "PB13", "PB14", "PB15", "PB16";
+       };
+       spi3_pins: spi3-pins {
+               function = "spi3";
+               pins = "PB17", "PB18", "PB19", "PB20", "PB21";
+       };
+       spi3_slave_pins: spi3-slave-pins {
+               function = "spi3";
+               pins = "PB18", "PB19", "PB20";
+       };
+       mclk0_pins: mclk0-pin {
+               function = "mclk0";
+               pins = "PB22";
+       };
+};

diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 6cc5980e2fa17911fb8f0af728a1012ce104efa5..0708771c193d064fa56be2c7f6115672b5c24d8d 100644 (file)
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -5,7 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 
-#include "eyeq5-fixed-clocks.dtsi"
+#include "eyeq5-clocks.dtsi"
 
 / {
        #address-cells = <2>;
@@ -78,6 +78,9 @@
                        interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
                        clocks  = <&uart_clk>, <&occ_periph>;
                        clock-names = "uartclk", "apb_pclk";
+                       resets = <&olb 0 10>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart0_pins>;
                };
 
                uart1: serial@900000 {
@@ -88,6 +91,9 @@
                        interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
                        clocks  = <&uart_clk>, <&occ_periph>;
                        clock-names = "uartclk", "apb_pclk";
+                       resets = <&olb 0 11>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart1_pins>;
                };
 
                uart2: serial@a00000 {
@@ -98,6 +104,18 @@
                        interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
                        clocks  = <&uart_clk>, <&occ_periph>;
                        clock-names = "uartclk", "apb_pclk";
+                       resets = <&olb 0 12>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart2_pins>;
+               };
+
+               olb: system-controller@e00000 {
+                       compatible = "mobileye,eyeq5-olb", "syscon";
+                       reg = <0 0xe00000 0x0 0x400>;
+                       #reset-cells = <2>;
+                       #clock-cells = <1>;
+                       clocks = <&xtal>;
+                       clock-names = "ref";
                };
 
                gic: interrupt-controller@140000 {
@@ -122,3 +140,5 @@
                };
        };
 };
+
+#include "eyeq5-pins.dtsi"