drm/amd/display: Don't set dram clock change requirement for SubVP

[Description]
In general cases we want to keep the dram clock change requirement (we
prefer configs that support MCLK switch). Only override to false for
SubVP.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index f913daabcca5aa2db110969e27522e476d8adeca..92d87745d933937806bf2a1fd27552cfe1059f8b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2984,6 +2984,7 @@ int dcn32_populate_dml_pipes_from_context(
        int i, pipe_cnt;
        struct resource_context *res_ctx = &context->res_ctx;
        struct pipe_ctx *pipe;
+       bool subvp_in_use = false;
 
        dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
 
@@ -3006,6 +3007,7 @@ int dcn32_populate_dml_pipes_from_context(
                switch (pipe->stream->mall_stream_config.type) {
                case SUBVP_MAIN:
                        pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
+                       subvp_in_use = true;
                        break;
                case SUBVP_PHANTOM:
                        pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
@@ -3076,6 +3078,14 @@ int dcn32_populate_dml_pipes_from_context(
 
        dcn32_update_det_override_for_mpo(dc, context, pipes);
 
+       // In general cases we want to keep the dram clock change requirement
+       // (prefer configs that support MCLK switch). Only override to false
+       // for SubVP
+       if (subvp_in_use)
+               context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
+       else
+               context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
+
        return pipe_cnt;
 }