#include <plat/devs.h>
 #include <plat/regs-serial.h>
 
-static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
-       [0] = {
-               .name           = "uclk1",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-};
-
 /* uart registration process */
 void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        u32 ucnt;
 
        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-               if (!tcfg->clocks) {
-                       tcfg->has_fracval = 1;
-                       tcfg->clocks = exynos4_serial_clocks;
-                       tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
-               }
+               tcfg->has_fracval = 1;
                tcfg->flags |= NO_NEED_CHECK_CLKSRC;
        }
 
 
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
-       [0] = {
-               .name           = "uclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-       [1] = {
-               .name           = "pclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       }
-};
-
-
 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = bast_serial_clocks,
-               .clocks_size = ARRAY_SIZE(bast_serial_clocks),
        },
        [1] = {
                .hwport      = 1,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = bast_serial_clocks,
-               .clocks_size = ARRAY_SIZE(bast_serial_clocks),
        },
        /* port 2 is not actually used */
        [2] = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = bast_serial_clocks,
-               .clocks_size = ARRAY_SIZE(bast_serial_clocks),
        }
 };
 
 
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-/* uart clock source(s) */
-
-static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
-       [0] = {
-               .name           = "uclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-       [1] = {
-               .name           = "pclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0.
-       }
-};
-
 static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = vr1000_serial_clocks,
-               .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
        },
        [1] = {
                .hwport      = 1,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = vr1000_serial_clocks,
-               .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
        },
        /* port 2 is not actually used */
        [2] = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = vr1000_serial_clocks,
-               .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
-
        }
 };
 
 
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
-       [0] = {
-               .name           = "uclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-       [1] = {
-               .name           = "pclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       }
-};
-
-
 static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = anubis_serial_clocks,
-               .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
        },
        [1] = {
                .hwport      = 2,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = anubis_serial_clocks,
-               .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
        },
 };
 
 
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
 
-static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
-       [0] = {
-               .name           = "uclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-       [1] = {
-               .name           = "pclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       }
-};
-
-
 static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = at2440evb_serial_clocks,
-               .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
        },
        [1] = {
                .hwport      = 1,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = at2440evb_serial_clocks,
-               .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
        },
 };
 
 
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 
-static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
-       [0] = {
-               .name           = "uclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-       [1] = {
-               .name           = "pclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       }
-};
-
 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = osiris_serial_clocks,
-               .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
        },
        [1] = {
                .hwport      = 1,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = osiris_serial_clocks,
-               .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
        },
        [2] = {
                .hwport      = 2,
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-               .clocks      = osiris_serial_clocks,
-               .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
        }
 };
 
 
 static struct map_desc rx1950_iodesc[] __initdata = {
 };
 
-static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
-       [0] = {
-              .name = "fclk_n",
-              .divisor = 1,
-              .min_baud = 0,
-              .max_baud = 0,
-       },
-};
-
 static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
        [0] = {
               .hwport = 0,
               .ucon = 0x3c5,
               .ulcon = 0x03,
               .ufcon = 0x51,
-              .clocks = rx1950_serial_clocks,
-              .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+               .clk_sel = S3C2410_UCON_CLKSEL3,
        },
        [1] = {
               .hwport = 1,
               .ucon = 0x3c5,
               .ulcon = 0x03,
               .ufcon = 0x51,
-              .clocks = rx1950_serial_clocks,
-              .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+               .clk_sel = S3C2410_UCON_CLKSEL3,
        },
        /* IR port */
        [2] = {
               .ucon = 0x3c5,
               .ulcon = 0x43,
               .ufcon = 0xf1,
-              .clocks = rx1950_serial_clocks,
-              .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+               .clk_sel = S3C2410_UCON_CLKSEL3,
        },
 };
 
 
        },
 };
 
-
-static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
-       [0] = {
-               .name           = "fclk_n",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       }
-};
-
 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
        [0] = {
                .hwport      = 0,
                .ucon        = 0x3c5,
                .ulcon       = 0x03,
                .ufcon       = 0x51,
-               .clocks      = rx3715_serial_clocks,
-               .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL3,
        },
        [1] = {
                .hwport      = 1,
                .ucon        = 0x3c5,
                .ulcon       = 0x03,
                .ufcon       = 0x00,
-               .clocks      = rx3715_serial_clocks,
-               .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL3,
        },
        /* IR port */
        [2] = {
                .ucon        = 0x3c5,
                .ulcon       = 0x43,
                .ufcon       = 0x51,
-               .clocks      = rx3715_serial_clocks,
-               .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+               .clk_sel        = S3C2410_UCON_CLKSEL3,
        }
 };
 
 
 #include <plat/s5p6450.h>
 #include <plat/regs-serial.h>
 
-static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
-       [0] = {
-               .name           = "pclk_low",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-       [1] = {
-               .name           = "uclk1",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-};
-
 /* uart registration process */
-
-void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-       struct s3c2410_uartcfg *tcfg = cfg;
-       u32 ucnt;
-
-       for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-               if (!tcfg->clocks) {
-                       tcfg->clocks = s5p64x0_serial_clocks;
-                       tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
-               }
-       }
-}
-
 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        int uart;
                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
        }
 
-       s5p64x0_common_init_uarts(cfg, no);
        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
-       s5p64x0_common_init_uarts(cfg, no);
        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
 #include <plat/s5pv210.h>
 #include <plat/regs-serial.h>
 
-static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = {
-       [0] = {
-               .name           = "pclk",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-};
-
 /* uart registration process */
 void __init s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
-       struct s3c2410_uartcfg *tcfg = cfg;
-       u32 ucnt;
-
-       for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-               if (!tcfg->clocks) {
-                       tcfg->clocks = s5pv210_serial_clocks;
-                       tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks);
-               }
-       }
-
        s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
 }
 
 
 #ifndef __ASSEMBLY__
 
-/* struct s3c24xx_uart_clksrc
- *
- * this structure defines a named clock source that can be used for the
- * uart, so that the best clock can be selected for the requested baud
- * rate.
- *
- * min_baud and max_baud define the range of baud-rates this clock is
- * acceptable for, if they are both zero, it is assumed any baud rate that
- * can be generated from this clock will be used.
- *
- * divisor gives the divisor from the clock to the one seen by the uart
-*/
-
-struct s3c24xx_uart_clksrc {
-       const char      *name;
-       unsigned int     divisor;
-       unsigned int     min_baud;
-       unsigned int     max_baud;
-};
-
 /* configuration structure for per-machine configurations for the
  * serial port
  *
        unsigned long      ucon;         /* value of ucon for port */
        unsigned long      ulcon;        /* value of ulcon for port */
        unsigned long      ufcon;        /* value of ufcon for port */
-
-       struct s3c24xx_uart_clksrc *clocks;
-       unsigned int                clocks_size;
 };
 
 /* s3c24xx_uart_devs
 
        unsigned int                    tx_irq;
 
        struct s3c24xx_uart_info        *info;
-       struct s3c24xx_uart_clksrc      *clksrc;
        struct clk                      *clk;
        struct clk                      *baudclk;
        struct uart_port                port;