net: dsa: qca8k: add explicit SGMII PLL enable

Support enabling PLL on the SGMII CPU port. Some device require this
special configuration or no traffic is transmitted and the switch
doesn't work at all. A dedicated binding is added to the CPU node
port to apply the correct reg on mac config.
Fail to correctly configure sgmii with qca8327 switch and warn if pll is
used on qca8337 with a revision greater than 1.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 67999d3619e8ce4aa49fed3cfb3d63ac332ff81e..e0a16fe6a298fcb1cea35c42d9bcdd98928ee3be 100644 (file)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1002,6 +1002,18 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
                        if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
                                priv->sgmii_rx_clk_falling_edge = true;
 
+                       if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
+                               priv->sgmii_enable_pll = true;
+
+                               if (priv->switch_id == QCA8K_ID_QCA8327) {
+                                       dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
+                                       priv->sgmii_enable_pll = false;
+                               }
+
+                               if (priv->switch_revision < 2)
+                                       dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
+                       }
+
                        break;
                default:
                        continue;
@@ -1312,8 +1324,11 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
                if (ret)
                        return;
 
-               val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
-                       QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
+               val |= QCA8K_SGMII_EN_SD;
+
+               if (priv->sgmii_enable_pll)
+                       val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
+                              QCA8K_SGMII_EN_TX;
 
                if (dsa_is_cpu_port(ds, port)) {
                        /* CPU port, we're talking to the CPU MAC, be a PHY */

diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 5eb0c890dfe4d5ee934db18fc83d32cf20907e99..77b1677edafa897d4d91eda2d685d84bfdfc2c1b 100644 (file)
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -266,6 +266,7 @@ struct qca8k_priv {
        u8 switch_revision;
        bool sgmii_rx_clk_falling_edge;
        bool sgmii_tx_clk_falling_edge;
+       bool sgmii_enable_pll;
        u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
        u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
        bool legacy_phy_port_mapping;