Revert "drm/amd/display: Correct hubp GfxVersion verification"

This reverts commit 3303aa64e7a6 ("drm/amd/display: Correct hubp GfxVersion verification")

Reason for revert: Got blank screen issues while doing PNP

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index 78c866688c61565bb501b64afbfef9c4be8ebb6b..e697d9bf1b44cfd5d0d6cec0526c9cf11320fd4d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -145,26 +145,21 @@ void hubp1_program_tiling(
 {
        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
-       ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
-
-       if (info->gfxversion == DcGfxVersion9) {
-               REG_UPDATE_6(DCSURF_ADDR_CONFIG,
-                               NUM_PIPES, log_2(info->gfx9.num_pipes),
-                               NUM_BANKS, log_2(info->gfx9.num_banks),
-                               PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
-                               NUM_SE, log_2(info->gfx9.num_shader_engines),
-                               NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
-                               MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
-
-               REG_UPDATE_4(DCSURF_TILING_CONFIG,
-                               SW_MODE, info->gfx9.swizzle,
-                               META_LINEAR, info->gfx9.meta_linear,
-                               RB_ALIGNED, info->gfx9.rb_aligned,
-                               PIPE_ALIGNED, info->gfx9.pipe_aligned);
-       } else {
-               hubp1_clear_tiling(&hubp1->base);
-       }
-
+       ASSERT(info->gfxversion == DcGfxVersion9);
+
+       REG_UPDATE_6(DCSURF_ADDR_CONFIG,
+                       NUM_PIPES, log_2(info->gfx9.num_pipes),
+                       NUM_BANKS, log_2(info->gfx9.num_banks),
+                       PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
+                       NUM_SE, log_2(info->gfx9.num_shader_engines),
+                       NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
+                       MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
+
+       REG_UPDATE_4(DCSURF_TILING_CONFIG,
+                       SW_MODE, info->gfx9.swizzle,
+                       META_LINEAR, info->gfx9.meta_linear,
+                       RB_ALIGNED, info->gfx9.rb_aligned,
+                       PIPE_ALIGNED, info->gfx9.pipe_aligned);
 }
 
 void hubp1_program_size(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index aaa8f8cf6c3037356d68df247ccceb15883064ea..4715e60e812ac68584698bbafb5828d97ea2f2cd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -313,22 +313,18 @@ static void hubp2_program_tiling(
        const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
-       ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
-
-       if (info->gfxversion == DcGfxVersion9) {
-               REG_UPDATE_3(DCSURF_ADDR_CONFIG,
-                               NUM_PIPES, log_2(info->gfx9.num_pipes),
-                               PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
-                               MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
-
-               REG_UPDATE_4(DCSURF_TILING_CONFIG,
-                               SW_MODE, info->gfx9.swizzle,
-                               META_LINEAR, 0,
-                               RB_ALIGNED, 0,
-                               PIPE_ALIGNED, 0);
-       } else {
-               hubp2_clear_tiling(&hubp2->base);
-       }
+       ASSERT(info->gfxversion == DcGfxVersion9);
+
+       REG_UPDATE_3(DCSURF_ADDR_CONFIG,
+                       NUM_PIPES, log_2(info->gfx9.num_pipes),
+                       PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
+                       MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
+
+       REG_UPDATE_4(DCSURF_TILING_CONFIG,
+                       SW_MODE, info->gfx9.swizzle,
+                       META_LINEAR, 0,
+                       RB_ALIGNED, 0,
+                       PIPE_ALIGNED, 0);
 }
 
 void hubp2_program_size(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
index 2126830a5a9e1966fc64926ff6d02e5146a9b719..207c2f86b7d78a2284c847ab8a2d5eb1e88035fb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
@@ -321,22 +321,18 @@ void hubp3_program_tiling(
        const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
-       ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
-
-       if (info->gfxversion == DcGfxVersion9) {
-               REG_UPDATE_4(DCSURF_ADDR_CONFIG,
-                       NUM_PIPES, log_2(info->gfx9.num_pipes),
-                       PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
-                       MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
-                       NUM_PKRS, log_2(info->gfx9.num_pkrs));
-
-               REG_UPDATE_3(DCSURF_TILING_CONFIG,
-                               SW_MODE, info->gfx9.swizzle,
-                               META_LINEAR, info->gfx9.meta_linear,
-                               PIPE_ALIGNED, info->gfx9.pipe_aligned);
-       } else {
-               hubp3_clear_tiling(&hubp2->base);
-       }
+       ASSERT(info->gfxversion == DcGfxVersion9);
+
+       REG_UPDATE_4(DCSURF_ADDR_CONFIG,
+               NUM_PIPES, log_2(info->gfx9.num_pipes),
+               PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
+               MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
+               NUM_PKRS, log_2(info->gfx9.num_pkrs));
+
+       REG_UPDATE_3(DCSURF_TILING_CONFIG,
+                       SW_MODE, info->gfx9.swizzle,
+                       META_LINEAR, info->gfx9.meta_linear,
+                       PIPE_ALIGNED, info->gfx9.pipe_aligned);
 
 }