Revert "drm/amd/display: Add Gfx Base Case For Linear Tiling Handling"

This reverts commit 08a01ec306db ("drm/amd/display: Add Gfx Base Case For Linear Tiling Handling")

Reason for revert: Got blank screen issues while doing PNP

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ef9df52dd34bf09fd257097404abc34eb9eebda5..9a9f8362811f1aa38d7d84b66101e829cf2a7458 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8040,7 +8040,6 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,
        dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
        dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
        dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
-       dc_plane_state->tiling_info.gfxversion = DcGfxVersion9;
        dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
        dc_plane_state->rotation = ROTATION_ANGLE_0;
        dc_plane_state->is_tiling_rotated = false;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6f3c283431d439bb08814b9a3b45cfb71f0ab59f..984b4bc5f53c6a732156f5a778e12750dcc362f0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2770,7 +2770,6 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct
                case DcGfxVersion7:
                case DcGfxVersion8:
                case DcGfxVersionUnknown:
-               case DcGfxBase:
                default:
                        break;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index a13d9d7dd6c5057528b8c891e9895ada4d1c0541..052d573408c3eb88e5d16067602755817d2601f0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -2065,13 +2065,6 @@ void get_surface_tile_visual_confirm_color(
        while (bottom_pipe_ctx->bottom_pipe != NULL)
                bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
 
-       if (bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxBase) {
-               /* LINEAR Surface - set border color to red */
-               color->color_r_cr = color_value;
-               return;
-       }
-
-       ASSERT(bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9);
        switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
        case DC_SW_LINEAR:
                /* LINEAR Surface - set border color to red */

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 639831295b219129d3320c498aa60ffab350cc3b..03d125f794b058235b635f0a6397e7a420c80722 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -4434,7 +4434,6 @@ enum dc_status dc_validate_global_state(
 
                        if (dc->res_pool->funcs->patch_unknown_plane_state &&
                                        pipe_ctx->plane_state &&
-                                       pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9 &&
                                        pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
                                result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
                                if (result != DC_OK)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 7121629da38ed9a88ddb44210497eb774736307a..cfa569a7bff1bb109c1a9501061efcdb241767df 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -342,8 +342,7 @@ enum swizzle_mode_addr3_values {
 };
 
 enum dc_gfxversion {
-       DcGfxBase = 0,
-       DcGfxVersion7,
+       DcGfxVersion7 = 0,
        DcGfxVersion8,
        DcGfxVersion9,
        DcGfxVersion10,

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 5df58fadc8621061f24a1051e49c0a63d5361da9..1c2009e38aa125f67c0b72c18d7236abb9640fda 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -100,7 +100,6 @@ static enum mi_bits_per_pixel get_mi_bpp(
 static enum mi_tiling_format get_mi_tiling(
                struct dc_tiling_info *tiling_info)
 {
-       ASSERT(tiling_info->gfxversion == DcGfxVersion8);
        switch (tiling_info->gfx8.array_mode) {
        case DC_ARRAY_1D_TILED_THIN1:
        case DC_ARRAY_1D_TILED_THICK:
@@ -434,7 +433,6 @@ static void program_tiling(
        struct dce_mem_input *dce_mi, const struct dc_tiling_info *info)
 {
        if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */
-               ASSERT(info->gfxversion == DcGfxVersion9);
                REG_UPDATE_6(GRPH_CONTROL,
                                GRPH_SW_MODE, info->gfx9.swizzle,
                                GRPH_NUM_BANKS, log_2(info->gfx9.num_banks),
@@ -449,7 +447,6 @@ static void program_tiling(
        }
 
        if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */
-               ASSERT(info->gfxversion == DcGfxVersion8);
                REG_UPDATE_9(GRPH_CONTROL,
                                GRPH_NUM_BANKS, info->gfx8.num_banks,
                                GRPH_BANK_WIDTH, info->gfx8.bank_width,

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 67cfca3361fb93bbedc4c75255515fd28dd6c692..2c43c24226385d4cbd6911d75f69192c027811bb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -165,8 +165,6 @@ static void program_tiling(
        const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
-       ASSERT(info->gfxversion == DcGfxVersion8);
-
        uint32_t value = 0;
 
        set_reg_field_value(value, info->gfx8.num_banks,
@@ -543,7 +541,6 @@ static const unsigned int *get_dvmm_hw_setting(
        else
                bpp = bpp_8;
 
-       ASSERT(tiling_info->gfxversion == DcGfxVersion8);
        switch (tiling_info->gfx8.array_mode) {
        case DC_ARRAY_1D_TILED_THIN1:
        case DC_ARRAY_1D_TILED_THICK:

diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index 71eeee02c0fa5b5293a7b8d7679e84cbab39bf31..74962791302f653ae83d0b632c8d00b85eaa4c78 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -1006,7 +1006,6 @@ bool dcn_validate_bandwidth(
 
                        v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
                                        pipe->plane_state->format);
-                       ASSERT(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9);
                        v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
                                        pipe->plane_state->tiling_info.gfx9.swizzle);
                        v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index e697d9bf1b44cfd5d0d6cec0526c9cf11320fd4d..6378e3fd72494c7d03f56d806e1def8368f60c40 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -145,8 +145,6 @@ void hubp1_program_tiling(
 {
        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
-       ASSERT(info->gfxversion == DcGfxVersion9);
-
        REG_UPDATE_6(DCSURF_ADDR_CONFIG,
                        NUM_PIPES, log_2(info->gfx9.num_pipes),
                        NUM_BANKS, log_2(info->gfx9.num_banks),

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index 4715e60e812ac68584698bbafb5828d97ea2f2cd..92288de4cc10c312959c6179dcb8251ec1e15ed6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -313,8 +313,6 @@ static void hubp2_program_tiling(
        const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
-       ASSERT(info->gfxversion == DcGfxVersion9);
-
        REG_UPDATE_3(DCSURF_ADDR_CONFIG,
                        NUM_PIPES, log_2(info->gfx9.num_pipes),
                        PIPE_INTERLEAVE, info->gfx9.pipe_interleave,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
index 207c2f86b7d78a2284c847ab8a2d5eb1e88035fb..0cc6f455898981e3f4c147c42641cc662b0d8227 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
@@ -321,8 +321,6 @@ void hubp3_program_tiling(
        const struct dc_tiling_info *info,
        const enum surface_pixel_format pixel_format)
 {
-       ASSERT(info->gfxversion == DcGfxVersion9);
-
        REG_UPDATE_4(DCSURF_ADDR_CONFIG,
                NUM_PIPES, log_2(info->gfx9.num_pipes),
                PIPE_INTERLEAVE, info->gfx9.pipe_interleave,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
index 861e940250af2440064a468dd591104b3127e4f3..c205500290ecd7d3af50affafd92b39af589709f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -589,12 +589,7 @@ void hubp401_program_tiling(
         *
         * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D dimension) which is HW default.
         */
-        if (info->gfxversion == DcGfxAddr3) {
-               REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle);
-       } else {
-               /* linear */
-               REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, 0);
-       }
+        REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle);
 }
 
 void hubp401_program_size(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
index 7d99f5d79e6dc0075185bd868be3f39c6d20ef7c..f5a4e97c40ced260157fe1aef6b11015b43d98fa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
@@ -401,8 +401,7 @@ void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
         */
        if (pipe_cnt == 1) {
                pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;
-               if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfxversion != DcGfxBase &&
-                       !(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9 && pipe->plane_state->tiling_info.gfx9.swizzle == DC_SW_LINEAR)) {
+               if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
                        if (!is_dual_plane(pipe->plane_state->format)) {
                                pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
                                pipes[0].pipe.src.unbounded_req_mode = true;