arm64: dts: imx8qm-mek: Add PCIe and SATA

Add PCIe[a,b] and SATA support for i.MX8QM-MEK board.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 62203eed6a6cb144dde3cfc59173f74e8f068ccb..e983633a4bb3171cf1065e7f80e926822d8bb914 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -181,6 +181,17 @@
                vin-supply = <&reg_can2_en>;
        };
 
+       reg_pciea: regulator-pcie {
+               compatible = "regulator-fixed";
+               pinctrl-0 = <&pinctrl_pciea_reg>;
+               pinctrl-names = "default";
+               regulator-max-microvolt = <3300000>;
+               regulator-min-microvolt = <3300000>;
+               regulator-name = "mpcie_3v3";
+               gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
        reg_vref_1v8: regulator-adc-vref {
                compatible = "regulator-fixed";
                regulator-name = "vref_1v8";
@@ -296,6 +307,12 @@
        status = "okay";
 };
 
+&hsio_phy {
+       fsl,hsio-cfg = "pciea-pcieb-sata";
+       fsl,refclk-pad-mode = "input";
+       status = "okay";
+};
+
 &i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;
@@ -541,6 +558,25 @@
        status = "okay";
 };
 
+&pciea {
+       phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
+       phy-names = "pcie-phy";
+       pinctrl-0 = <&pinctrl_pciea>;
+       pinctrl-names = "default";
+       reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
+       vpcie-supply = <&reg_pciea>;
+       status = "okay";
+};
+
+&pcieb {
+       phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
+       phy-names = "pcie-phy";
+       pinctrl-0 = <&pinctrl_pcieb>;
+       pinctrl-names = "default";
+       reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
+       status = "disabled";
+};
+
 &qm_pwm_lvds0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm_lvds0>;
@@ -640,6 +676,10 @@
        status = "okay";
 };
 
+&sata {
+       status = "okay";
+};
+
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
@@ -829,6 +869,28 @@
                >;
        };
 
+       pinctrl_pciea: pcieagrp {
+               fsl,pins = <
+                       IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28                0x04000021
+                       IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29               0x06000021
+                       IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K        0x20
+               >;
+       };
+
+       pinctrl_pciea_reg: pcieareggrp {
+               fsl,pins = <
+                       IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13                   0x06000021
+               >;
+       };
+
+       pinctrl_pcieb: pciebgrp {
+               fsl,pins = <
+                       IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B          0x06000021
+                       IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31                0x04000021
+                       IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00               0x06000021
+               >;
+       };
+
        pinctrl_pwm_lvds0: pwmlvds0grp {
                fsl,pins = <
                        IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT              0x00000020