arm64: dts: qcom: sa8775p: add DisplayPort device nodes

Add device tree nodes for the DPTX0 and DPTX1 controllers
with their corresponding PHYs found on Qualcomm SA8775P SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Link: https://lore.kernel.org/r/20241125105747.6595-2-quic_mukhopad@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 09873524c1b3ddb7a58d6a846b35be21bf9a365b..cc598e98983f5a28af0b9482d18aff5bbe423efb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3864,6 +3864,27 @@
                                interrupt-parent = <&mdss0>;
                                interrupts = <0>;
 
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               dpu_intf0_out: endpoint {
+                                                       remote-endpoint = <&mdss0_dp0_in>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               dpu_intf4_out: endpoint {
+                                                       remote-endpoint = <&mdss0_dp1_in>;
+                                               };
+                                       };
+                               };
+
                                mdss0_mdp_opp_table: opp-table {
                                        compatible = "operating-points-v2";
 
@@ -3888,6 +3909,202 @@
                                        };
                                };
                        };
+
+                       mdss0_dp0_phy: phy@aec2a00 {
+                               compatible = "qcom,sa8775p-edp-phy";
+
+                               reg = <0x0 0x0aec2a00 0x0 0x200>,
+                                     <0x0 0x0aec2200 0x0 0xd0>,
+                                     <0x0 0x0aec2600 0x0 0xd0>,
+                                     <0x0 0x0aec2000 0x0 0x1c8>;
+
+                               clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+                               clock-names = "aux",
+                                             "cfg_ahb";
+
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+
+                               status = "disabled";
+                       };
+
+                       mdss0_dp1_phy: phy@aec5a00 {
+                               compatible = "qcom,sa8775p-edp-phy";
+
+                               reg = <0x0 0x0aec5a00 0x0 0x200>,
+                                     <0x0 0x0aec5200 0x0 0xd0>,
+                                     <0x0 0x0aec5600 0x0 0xd0>,
+                                     <0x0 0x0aec5000 0x0 0x1c8>;
+
+                               clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+                               clock-names = "aux",
+                                             "cfg_ahb";
+
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+
+                               status = "disabled";
+                       };
+
+                       mdss0_dp0: displayport-controller@af54000 {
+                               compatible = "qcom,sa8775p-dp";
+
+                               reg = <0x0 0x0af54000 0x0 0x104>,
+                                     <0x0 0x0af54200 0x0 0x0c0>,
+                                     <0x0 0x0af55000 0x0 0x770>,
+                                     <0x0 0x0af56000 0x0 0x09c>,
+                                     <0x0 0x0af57000 0x0 0x09c>;
+
+                               interrupt-parent = <&mdss0>;
+                               interrupts = <12>;
+
+                               clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                               clock-names = "core_iface",
+                                             "core_aux",
+                                             "ctrl_link",
+                                             "ctrl_link_iface",
+                                             "stream_pixel";
+                               assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+                                                 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                               assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
+                               phys = <&mdss0_dp0_phy>;
+                               phy-names = "dp";
+
+                               operating-points-v2 = <&dp_opp_table>;
+                               power-domains = <&rpmhpd SA8775P_MMCX>;
+
+                               #sound-dai-cells = <0>;
+
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               mdss0_dp0_in: endpoint {
+                                                       remote-endpoint = <&dpu_intf0_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mdss0_dp0_out: endpoint { };
+                                       };
+                               };
+
+                               dp_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-160000000 {
+                                               opp-hz = /bits/ 64 <160000000>;
+                                               required-opps = <&rpmhpd_opp_low_svs>;
+                                       };
+
+                                       opp-270000000 {
+                                               opp-hz = /bits/ 64 <270000000>;
+                                               required-opps = <&rpmhpd_opp_svs>;
+                                       };
+
+                                       opp-540000000 {
+                                               opp-hz = /bits/ 64 <540000000>;
+                                               required-opps = <&rpmhpd_opp_svs_l1>;
+                                       };
+
+                                       opp-810000000 {
+                                               opp-hz = /bits/ 64 <810000000>;
+                                               required-opps = <&rpmhpd_opp_nom>;
+                                       };
+                               };
+                       };
+
+                       mdss0_dp1: displayport-controller@af5c000 {
+                               compatible = "qcom,sa8775p-dp";
+
+                               reg = <0x0 0x0af5c000 0x0 0x104>,
+                                     <0x0 0x0af5c200 0x0 0x0c0>,
+                                     <0x0 0x0af5d000 0x0 0x770>,
+                                     <0x0 0x0af5e000 0x0 0x09c>,
+                                     <0x0 0x0af5f000 0x0 0x09c>;
+
+                               interrupt-parent = <&mdss0>;
+                               interrupts = <13>;
+
+                               clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+                               clock-names = "core_iface",
+                                             "core_aux",
+                                             "ctrl_link",
+                                             "ctrl_link_iface",
+                                             "stream_pixel";
+                               assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+                                                 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+                               assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
+                               phys = <&mdss0_dp1_phy>;
+                               phy-names = "dp";
+
+                               operating-points-v2 = <&dp1_opp_table>;
+                               power-domains = <&rpmhpd SA8775P_MMCX>;
+
+                               #sound-dai-cells = <0>;
+
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               mdss0_dp1_in: endpoint {
+                                                       remote-endpoint = <&dpu_intf4_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mdss0_dp1_out: endpoint { };
+                                       };
+                               };
+
+                               dp1_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-160000000 {
+                                               opp-hz = /bits/ 64 <160000000>;
+                                               required-opps = <&rpmhpd_opp_low_svs>;
+                                       };
+
+                                       opp-270000000 {
+                                               opp-hz = /bits/ 64 <270000000>;
+                                               required-opps = <&rpmhpd_opp_svs>;
+                                       };
+
+                                       opp-540000000 {
+                                               opp-hz = /bits/ 64 <540000000>;
+                                               required-opps = <&rpmhpd_opp_svs_l1>;
+                                       };
+
+                                       opp-810000000 {
+                                               opp-hz = /bits/ 64 <810000000>;
+                                               required-opps = <&rpmhpd_opp_nom>;
+                                       };
+                               };
+                       };
                };
 
                dispcc0: clock-controller@af00000 {
@@ -3897,7 +4114,8 @@
                                 <&rpmhcc RPMH_CXO_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK_A>,
                                 <&sleep_clk>,
-                                <0>, <0>, <0>, <0>,
+                                <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
+                                <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
                                 <0>, <0>, <0>, <0>;
                        power-domains = <&rpmhpd SA8775P_MMCX>;
                        #clock-cells = <1>;