/* minimum number of free TX descriptors required to wake up TX process */
 #define TG3_TX_WAKEUP_THRESH(tnapi)            ((tnapi)->tx_pending / 4)
+#define TG3_TX_BD_DMA_MAX              4096
 
 #define TG3_RAW_IP_ALIGN 2
 
        if (tg3_40bit_overflow_test(tp, map, len))
                hwbug = 1;
 
-       if (*budget) {
+       if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
+               u32 tmp_flag = flags & ~TXD_FLAG_END;
+               while (len > TG3_TX_BD_DMA_MAX) {
+                       u32 frag_len = TG3_TX_BD_DMA_MAX;
+                       len -= TG3_TX_BD_DMA_MAX;
+
+                       if (len) {
+                               tnapi->tx_buffers[*entry].fragmented = true;
+                               /* Avoid the 8byte DMA problem */
+                               if (len <= 8) {
+                                       len += TG3_TX_BD_DMA_MAX / 2;
+                                       frag_len = TG3_TX_BD_DMA_MAX / 2;
+                               }
+                       } else
+                               tmp_flag = flags;
+
+                       if (*budget) {
+                               tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
+                                             frag_len, tmp_flag, mss, vlan);
+                               (*budget)--;
+                               *entry = NEXT_TX(*entry);
+                       } else {
+                               hwbug = 1;
+                               break;
+                       }
+
+                       map += frag_len;
+               }
+
+               if (len) {
+                       if (*budget) {
+                               tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
+                                             len, flags, mss, vlan);
+                               (*budget)--;
+                               *entry = NEXT_TX(*entry);
+                       } else {
+                               hwbug = 1;
+                       }
+               }
+       } else {
                tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
                              len, flags, mss, vlan);
-               (*budget)--;
-       } else
-               hwbug = 1;
-
-       *entry = NEXT_TX(*entry);
+               *entry = NEXT_TX(*entry);
+       }
 
        return hwbug;
 }
        if (tg3_flag(tp, 5755_PLUS))
                tg3_flag_set(tp, SHORT_DMA_BUG);
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+               tg3_flag_set(tp, 4K_FIFO_LIMIT);
+
        if (tg3_flag(tp, 5717_PLUS))
                tg3_flag_set(tp, LRG_PROD_RING_CAP);