clk: renesas: r8a7742: Add clk entry for VSPR

Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module
can be used on R8A7742 (RZ/G1H) SoC.

Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that
VSP1 clock names are in sync.

Note: The entry for VSPR clock was accidentally dropped from RZ/G manual
when all the information related to RT were removed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200831180312.7453-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a7742-cpg-mssr.c b/drivers/clk/renesas/r8a7742-cpg-mssr.c
index e919828668a4824c0a54adf6aa3d3f70d2a11a36..e541489bd1cd4a2322160fd0774839104f7d2c91 100644 (file)
--- a/drivers/clk/renesas/r8a7742-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c
@@ -97,7 +97,8 @@ static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
        DEF_MOD("tmu0",                  125,   R8A7742_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7742_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7742_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7742_CLK_ZS),
+       DEF_MOD("vspr",                  130,   R8A7742_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7742_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7742_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7742_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7742_CLK_MP),