#define   SKL_DFSM_CDCLK_LIMIT_540     (1 << 23)
 #define   SKL_DFSM_CDCLK_LIMIT_450     (2 << 23)
 #define   SKL_DFSM_CDCLK_LIMIT_337_5   (3 << 23)
+#define   ICL_DFSM_DMC_DISABLE         (1 << 23)
 #define   SKL_DFSM_PIPE_A_DISABLE      (1 << 30)
 #define   SKL_DFSM_PIPE_B_DISABLE      (1 << 21)
 #define   SKL_DFSM_PIPE_C_DISABLE      (1 << 28)
 
 
                if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
                        info->display.has_fbc = 0;
+
+               if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
+                       info->display.has_csr = 0;
        }
 
        /* Initialize slice/subslice/EU info */