From: Lijuan Gao <quic_lijuang@quicinc.com>
Date: Thu, 19 Dec 2024 07:59:47 +0000 (+0800)
Subject: arm64: dts: qcom: correct gpio-ranges for QCS615
X-Git-Tag: ceph-for-6.15-rc4~365^2~4^2~59
X-Git-Url: http://git.apps.os.sepia.ceph.com/?a=commitdiff_plain;h=80c82827327d80bde8fc96ebd4e637d0454062db;p=ceph-client.git

arm64: dts: qcom: correct gpio-ranges for QCS615

Correct the gpio-ranges for the QCS615 TLMM pin controller to include
GPIOs 0-122 and the UFS_RESET pin for primary UFS memory reset.

Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241219-correct_gpio_ranges-v2-5-19af8588dbd0@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 84a378487dcea..6f87e3072069b 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -938,7 +938,7 @@
 				    "west",
 				    "south";
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-			gpio-ranges = <&tlmm 0 0 123>;
+			gpio-ranges = <&tlmm 0 0 124>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;