From: WenLei <lei.wen2@zte.com.cn>
Date: Tue, 19 Aug 2025 07:12:25 +0000 (+0800)
Subject: common/Cycles: Add high-precision counter support for riscv64
X-Git-Tag: v21.0.0~50^2~94^2
X-Git-Url: http://git-server-git.apps.pok.os.sepia.ceph.com/?a=commitdiff_plain;h=f8fc29dfd5aed2c01728788114c3d69e133d8ea5;p=ceph.git

common/Cycles: Add high-precision counter support for riscv64

Signed-off-by: WenLei <lei.wen2@zte.com.cn>
---

diff --git a/src/common/Cycles.h b/src/common/Cycles.h
index b546479c2b35..f12ea092f494 100644
--- a/src/common/Cycles.h
+++ b/src/common/Cycles.h
@@ -84,6 +84,10 @@ class Cycles {
     uint64_t tsc;
     asm volatile("stck %0" : "=Q" (tsc) : : "cc");
     return tsc;
+#elif defined(__riscv) && __riscv_xlen == 64
+    uint64_t tsc;
+    asm volatile ("rdtime %0" : "=r" (tsc));
+    return tsc;
 #else
 #warning No high-precision counter available for your OS/arch
     return 0;