arch: add SSE3, SSSE3, SSSE41 and PCLMUL intel features

And add a note about valgrind forcing a fake cpuid.

Signed-off-by: Loic Dachary <loic@dachary.org>

diff --git a/src/arch/intel.c b/src/arch/intel.c
index 9f2d3e4ad4070341f6f17842d368f6a6e6ad3bcb..e487da4f9b855efa11efa9810fe160a5a911f324 100644 (file)
--- a/src/arch/intel.c
+++ b/src/arch/intel.c
@@ -1,11 +1,31 @@
+/*
+ * Ceph - scalable distributed file system
+ *
+ * Copyright (C) 2013,2014 Inktank Storage, Inc.
+ * Copyright (C) 2014 Cloudwatt <libre.licensing@cloudwatt.com>
+ *
+ * Author: Loic Dachary <loic@dachary.org>
+ *
+ *  This library is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU Lesser General Public
+ *  License as published by the Free Software Foundation; either
+ *  version 2.1 of the License, or (at your option) any later version.
+ * 
+ */
+#include <stdio.h>
 #include "arch/probe.h"
 
 /* flags we export */
+int ceph_arch_intel_pclmul = 0;
 int ceph_arch_intel_sse42 = 0;
+int ceph_arch_intel_sse41 = 0;
+int ceph_arch_intel_ssse3 = 0;
+int ceph_arch_intel_sse3 = 0;
 int ceph_arch_intel_sse2 = 0;
 
 #ifdef __x86_64__
 
+/* Note: valgrind redefines cpuid : it is different from the native processor. */
 /* intel cpu? */
 static void do_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx,
                      unsigned int *edx)
@@ -23,15 +43,36 @@ static void do_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx,
                 : "eax", "ebx", "ecx", "edx");
 }
 
+/* http://en.wikipedia.org/wiki/CPUID#EAX.3D1:_Processor_Info_and_Feature_Bits */
+
+#define CPUID_PCLMUL   (1 << 1)
+#define CPUID_SSE42    (1 << 20)
+#define CPUID_SSE41    (1 << 19)
+#define CPUID_SSSE3    (1 << 9)
+#define CPUID_SSE3     (1)
+#define CPUID_SSE2     (1 << 26)
+
 int ceph_arch_intel_probe(void)
 {
        /* i know how to check this on x86_64... */
        unsigned int eax = 1, ebx, ecx, edx;
        do_cpuid(&eax, &ebx, &ecx, &edx);
-       if ((ecx & (1 << 20)) != 0) {
+       if ((ecx & CPUID_PCLMUL) != 0) {
+               ceph_arch_intel_pclmul = 1;
+       }
+       if ((ecx & CPUID_SSE42) != 0) {
                ceph_arch_intel_sse42 = 1;
        }
-       if ((edx & (1 << 26)) != 0) {
+       if ((ecx & CPUID_SSE41) != 0) {
+               ceph_arch_intel_sse41 = 1;
+       }
+       if ((ecx & CPUID_SSSE3) != 0) {
+               ceph_arch_intel_ssse3 = 1;
+       }
+       if ((ecx & CPUID_SSE3) != 0) {
+               ceph_arch_intel_sse3 = 1;
+       }
+       if ((edx & CPUID_SSE2) != 0) {
                ceph_arch_intel_sse2 = 1;
        }
 

diff --git a/src/arch/intel.h b/src/arch/intel.h
index 7703bd76d3acdb33a295386de4bc72f50e28f70f..2c3b80995e07fc57ba98465413ad34ac6433dd09 100644 (file)
--- a/src/arch/intel.h
+++ b/src/arch/intel.h
@@ -5,7 +5,11 @@
 extern "C" {
 #endif
 
+extern int ceph_arch_intel_pclmul; /* true if we have PCLMUL features */
 extern int ceph_arch_intel_sse42;  /* true if we have sse 4.2 features */
+extern int ceph_arch_intel_sse41;  /* true if we have sse 4.1 features */
+extern int ceph_arch_intel_ssse3;  /* true if we have ssse 3 features */
+extern int ceph_arch_intel_sse3;   /* true if we have sse 3 features */
 extern int ceph_arch_intel_sse2;   /* true if we have sse 2 features */
 extern int ceph_arch_intel_probe(void);